From 9e55ff6a879ee6eb96988e52020c4c20a4898c4f Mon Sep 17 00:00:00 2001 From: Barnali Sarkar Date: Mon, 5 Jun 2017 20:01:14 +0530 Subject: soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/include/soc/iomap.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 0b52095879..a8e4bc9bc5 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,14 +25,14 @@ #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) -#define ACPI_PMIO_BASE 0x400 -#define ACPI_PMIO_SIZE 0x100 +#define ACPI_BASE_ADDRESS 0x400 +#define ACPI_BASE_SIZE 0x100 #define R_ACPI_PM1_TMR 0x8 /* CST Range (R/W) IO port block size */ #define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 /* ACPI PMIO Offset to C-state register*/ -#define ACPI_PMIO_CST_REG (ACPI_PMIO_BASE + 0x14) +#define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14) /* Accesses to these BARs are hardcoded in FSP */ #define PMC_BAR0 0xfe042000 -- cgit v1.2.3