From 9d07910d24f4b372222a68087aa95caf332fb1dc Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 2 Feb 2018 15:11:29 -0800 Subject: soc/intel/apollolake: Clear RTC failure bit after reading it This change ensures that the RTC failure bit is cleared in PMCON1 after cmos_init checks for it. Before this change, RPS was cleared in dev init phase. If any reboot occurred before dev init stage (e.g. FSP reset) then RPS won't be cleared and cmos_init will re-initialize CMOS data. This resulted in any information like VBNV flags stored in CMOS after first cmos_init to be lost. BUG=b:72879807 BRANCH=coral TEST=Verified that recovery request is preserved when recovery is requested without battery on coral. Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/23578 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/include/soc/pm.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 34b9f965ae..e8ec645b1f 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -173,8 +173,13 @@ #define COLD_BOOT_STS (1 << 27) #define COLD_RESET_STS (1 << 26) #define WARM_RESET_STS (1 << 25) +#define GLOBAL_RESET_STS (1 << 24) #define SRS (1 << 20) +#define MS4V (1 << 18) #define RPS (1 << 2) +#define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \ + WARM_RESET_STS | GLOBAL_RESET_STS | \ + SRS | MS4V) #define GEN_PMCON2 0x1024 #define GEN_PMCON3 0x1028 # define SLP_S3_ASSERT_WIDTH_SHIFT 10 -- cgit v1.2.3