From 9c86aafe5a18068edb824faf4d2e44f0fefc6411 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 26 Apr 2017 15:02:51 -0500 Subject: soc/intel/apollolake: work around full retrain constraints on warm reset It's come to attention that apollolake doesn't support a full retrain on warm reset. Therefore force a cold reset when a full retrain is requested in the non-S5 path. BUG=b:37687843 Change-Id: If9a3de1fa8760e7bb2f06eef93a0deb9dbd3f047 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/19483 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/include/soc/pm.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index f754541bc2..7db63f6bdc 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -143,6 +143,9 @@ /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ #define PRSTS 0x1000 #define GEN_PMCON1 0x1020 +#define COLD_BOOT_STS (1 << 27) +#define COLD_RESET_STS (1 << 26) +#define WARM_RESET_STS (1 << 25) #define SRS (1 << 20) #define RPS (1 << 2) #define GEN_PMCON2 0x1024 -- cgit v1.2.3