From 93cdc8bbc20539cb9a2c1cbe3057c566cc5293e7 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Tue, 18 Apr 2017 15:42:09 -0700 Subject: soc/intel/apollolake: Use common PMC for apollolake With this patch apollolake uses the common PMC util code.No regression observed on a APL platform. Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2 Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/19375 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/include/soc/gpe.h | 1 + src/soc/intel/apollolake/include/soc/pm.h | 34 ++++-------------------------- 2 files changed, 5 insertions(+), 30 deletions(-) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h index 5482ed379f..7dfb6f5bd2 100644 --- a/src/soc/intel/apollolake/include/soc/gpe.h +++ b/src/soc/intel/apollolake/include/soc/gpe.h @@ -136,4 +136,5 @@ #define GPE0_DW3_30 126 #define GPE0_DW3_31 127 +#define GPE_MAX GPE0_DW3_31 #endif diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 4744b89814..3be39554ed 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -21,6 +21,8 @@ #include #include #include +#include +#include /* ACPI_BASE_ADDRESS */ @@ -135,6 +137,7 @@ #define GPE0_B 1 #define GPE0_C 2 #define GPE0_D 3 +#define GPE_STD GPE0_A #define SATA_PME_STS (1 << 17) #define SMB_WAK_STS (1 << 16) #define AVS_PME_STS (1 << 14) @@ -176,9 +179,7 @@ # define CF9_GLB_RST (1 << 20) #define GPIO_GPE_CFG 0x1050 #define GPE0_DWX_MASK 0xf -#define GPE0_DW1_SHIFT 4 -#define GPE0_DW2_SHIFT 8 -#define GPE0_DW3_SHIFT 12 +#define GPE0_DW_SHIFT(x) (4 + 4*(x)) #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) #define PMC_GPE_N_95_64 8 @@ -216,33 +217,6 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __packed; -int fill_power_state(struct chipset_power_state *ps); -int chipset_prev_sleep_state(struct chipset_power_state *ps); -/* Rewrite the gpe0 registers in cbmem to proper values as per routing table */ -void fixup_power_state(void); - -/* Power Management Utility Functions. */ -uint32_t clear_smi_status(void); -uint16_t clear_pm1_status(void); -uint32_t clear_tco_status(void); -uint32_t clear_gpe_status(void); -void clear_pmc_status(void); -void clear_gpi_gpe_sts(void); -uint32_t get_smi_en(void); -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); -void enable_pm1(uint16_t events); -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); -void disable_all_gpe(void); -uintptr_t get_pmc_mmio_bar(void); -void pmc_gpe_init(void); - -void global_reset_enable(bool enable); -void global_reset_lock(void); - void pch_log_state(void); void enable_pm_timer_emulation(void); -- cgit v1.2.3