From 87fb1a6cdbb58d5031f0dcf9b8ddf200df70a068 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Wed, 10 Feb 2016 17:47:03 -0800 Subject: soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/include/soc/bootblock.h | 2 ++ src/soc/intel/apollolake/include/soc/cpu.h | 24 +++++++++++++ src/soc/intel/apollolake/include/soc/northbridge.h | 26 ++++++++++++++ src/soc/intel/apollolake/include/soc/pci_devs.h | 40 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/uart.h | 28 +++++++++++++++ 5 files changed, 120 insertions(+) create mode 100644 src/soc/intel/apollolake/include/soc/cpu.h create mode 100644 src/soc/intel/apollolake/include/soc/northbridge.h create mode 100644 src/soc/intel/apollolake/include/soc/pci_devs.h create mode 100644 src/soc/intel/apollolake/include/soc/uart.h (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h index 933c7fecd4..655188bf62 100644 --- a/src/soc/intel/apollolake/include/soc/bootblock.h +++ b/src/soc/intel/apollolake/include/soc/bootblock.h @@ -3,4 +3,6 @@ #include void asmlinkage bootblock_c_entry(void); +/* provide prototype for lib/bootblock.c main as workaround */ +void main(void); #endif diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h new file mode 100644 index 0000000000..bee58b206e --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_CPU_H_ +#define _SOC_APOLLOLAKE_CPU_H_ + +#include + +#define CPUID_APOLLOLAKE_A0 0x506c8 + +#define MSR_PLATFORM_INFO 0xce + +#define BASE_CLOCK_MHZ 100 + +#endif /* _SOC_APOLLOLAKE_CPU_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h new file mode 100644 index 0000000000..4a071cb788 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/northbridge.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_ +#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_ + +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define PCIEX_SIZE (256 * MiB) + +#define BDSM 0xb0 /* Base Data Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ + +#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h new file mode 100644 index 0000000000..3116389090 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -0,0 +1,40 @@ +#ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_ +#define _SOC_APOLLOLAKE_PCI_DEVS_H_ + +#include + +#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0) +#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func) + + +#if ENV_RAMSTAGE +#include +#include +#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot)) +#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func)) +#else +#include +#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0) +#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func) +#endif + +/* North bridge devices */ +#define NB_DEV_SLOT_ROOT 0x00 +#define NB_DEVFN_ROOT _NB_DEVFN(ROOT) +#define NB_DEV_ROOT _NB_DEV(ROOT) + +/* LPSS UART */ +#define LPSS_DEV_SLOT_UART 0x18 +#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0) +#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1) +#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2) +#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3) +#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0) +#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1) +#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2) +#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3) + +#define P2SB_DEV PCI_DEV(0, 0xd, 0) +#define PMC_DEV PCI_DEV(0, 0xd, 1) + +#endif diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h new file mode 100644 index 0000000000..fd535fba23 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/uart.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_UART_H_ +#define _SOC_APOLLOLAKE_UART_H_ + +/* Clock is 100MHz * (M / N).*/ +#define UART_CLK 0x200 +# define UART_CLK_UPDATE (1 << 31) +# define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16) +# define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1) +# define UART_CLK_EN (1 << 0) +#define UART_RESET 0x204 +# define UART_RESET_DMA_EN (1 << 2) +# define UART_RESET_UART_EN (3 << 0) + +void lpss_console_uart_init(void); + +#endif /* _SOC_APOLLOLAKE_UART_H_ */ -- cgit v1.2.3