From 81d1e09113bc12ea9427e9522d4f5eab982c145e Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 13 Jul 2016 01:49:10 -0500 Subject: soc/intel/apollolake: work around FSP for gpio interrupt polarity FSP is currently setting a hard-coded policy for the interrupt polarity settings. When the mainboard has already set the GPIO settings up prior to SiliconInit being called that results in the previous settings being dropped. Work around FSP's default policy until FSP is fixed. BUG=chrome-os-partner:54955 Change-Id: Ibbd8c4894d8fbce479aeb73aa775b67df15dae85 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15649 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Andrey Petrov Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/include/soc/itss.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/itss.h b/src/soc/intel/apollolake/include/soc/itss.h index 1de722683e..2f47ec6259 100644 --- a/src/soc/intel/apollolake/include/soc/itss.h +++ b/src/soc/intel/apollolake/include/soc/itss.h @@ -16,7 +16,14 @@ #ifndef _SOC_APOLLOLAKE_ITSS_H_ #define _SOC_APOLLOLAKE_ITSS_H_ +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END 119 + /* Set the interrupt polarity for provided IRQ to the APIC. */ void itss_set_irq_polarity(int irq, int active_low); +/* Snapshot and restore IRQ polarity settings for the inclusive range. */ +void itss_snapshot_irq_polarities(int start, int end); +void itss_restore_irq_polarities(int start, int end); + #endif /* _SOC_APOLLOLAKE_ITSS_H_ */ -- cgit v1.2.3