From 752dc8e4258b708dc4a96b3d929163b1560492ae Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Wed, 12 Jul 2017 14:27:09 +0530 Subject: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros Rename BAR0 and BAR2 SRAM base and size macros to align with the spec. * PMC_SRAM_BASE_0 -> SRAM_BASE_0 * PMC_SRAM_SIZE_0 -> SRAM_SIZE_0 * PMC_SRAM_BASE_1 -> SRAM_BASE_2 * PMC_SRAM_SIZE_1 -> SRAM_SIZE_2 Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48 Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/20539 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/include/soc/iomap.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index a8e4bc9bc5..c3eb66bef6 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -39,10 +39,10 @@ #define PMC_BAR1 0xfe044000 #define PMC_BAR0_SIZE (8 * KiB) -#define PMC_SRAM_BASE_0 0xfe900000 -#define PMC_SRAM_SIZE_0 (8 * KiB) -#define PMC_SRAM_BASE_1 0xfe902000 -#define PMC_SRAM_SIZE_1 (4 * KiB) +#define SRAM_BASE_0 0xfe900000 +#define SRAM_SIZE_0 (8 * KiB) +#define SRAM_BASE_2 0xfe902000 +#define SRAM_SIZE_2 (4 * KiB) /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 -- cgit v1.2.3