From 6ac226d915ade86216d77316c77f824a07dd0e1c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 15 Jun 2016 17:13:20 -0700 Subject: intel/apollolake: Enable SPI properly in bootblock and ramstage Bootblock: - Temporary BAR needs to be assigned for SPI device until PCI enumeration is done by ramstage which allocates a new BAR. - Call spi_init to allow bootblock/verstage to write/erase on flash. Ramstage: - spi_init needs to run in ramstage to allow write protect to be disabled for eventlog and NVRAM updates. This needs to be done pretty early so that any init calls(e.g. mainboard_ec_init) writing to flash work properly. Verified with this change that there are no more flash write/erase errors for ELOG/NVRAM. BUG=chrome-os-partner:54283 Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/15209 Reviewed-by: Aaron Durbin Reviewed-by: Andrey Petrov Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/include/soc/iomap.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index e676ba5a7f..716c2a604f 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -30,4 +30,7 @@ #define PMC_BAR0 0xfe042000 #define PMC_BAR1 0xfe044000 +/* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ +#define PRERAM_SPI_BASE_ADDRESS 0xfe010000 + #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ -- cgit v1.2.3