From 1cf5b87f48668055e531a13c143abf697934dc80 Mon Sep 17 00:00:00 2001 From: "Nelson, Cole" Date: Fri, 11 Nov 2016 14:17:37 -0800 Subject: soc/intel/apollolake: Enable and Lock AES feature register Configure MPinit feature register during boot and s3 resume. Enable and Lock Advanced Encryption Standard (AES-NI) feature. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: Id16f62ec4e7463a466c43d67f2b03e07e324fa93 Signed-off-by: Venkateswarlu Vinjamuri Reviewed-on: https://review.coreboot.org/17396 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/include/soc/cpu.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 66fc29babc..38ce4ff913 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -66,6 +66,9 @@ void set_max_freq(void); #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL +#define FEATURE_CONFIG_LOCK (1 << 0) #define MSR_POWER_CTL 0x1fc #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) -- cgit v1.2.3