From 067d38a7af16bd6ca3add8d806874571fa1151c1 Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Thu, 31 May 2018 19:16:09 -0700 Subject: soc/intel/apollolake: Add Page table mapping for System Memory Since we do not know before hand the memory range initialized by FSP memory init until it completes and as memory gets accessed from within FSP memory init to migrate FSP from CAR to memory, we need to add this mapping in coreboot. Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/26745 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/glk_page_map.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/apollolake/glk_page_map.txt') diff --git a/src/soc/intel/apollolake/glk_page_map.txt b/src/soc/intel/apollolake/glk_page_map.txt index e4c51b0d50..e96a2db0ea 100644 --- a/src/soc/intel/apollolake/glk_page_map.txt +++ b/src/soc/intel/apollolake/glk_page_map.txt @@ -1,3 +1,9 @@ +0x00000000, 0x100000000, WB, # RAM +# Above entry is needed because below 4G allocated memory range is +# only known after FSP memory init completes. However, FSP migrates to memory +# from cache as ram before it exits FSP Memory Init. Hence we need to add +# page table entries for this entire range before FSP Memory Init. The +# overlapped MMIO ranges will be overridden by below entries. 0xd0000000, 0x100000000, UC, NX # All of MMIO # Maximum 16MiB of mmio SPI flash decode. 0xff000000, 0x100000000, WP, # memory-mapped SPI -- cgit v1.2.3