From ec7293652af797b2595bec396bae8cd625afbf8e Mon Sep 17 00:00:00 2001 From: Ravi Sarawadi Date: Fri, 9 Sep 2016 14:08:50 -0700 Subject: soc/apollolake: Add soc core init Add soc core init to set up the following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST= Check C-state functioning using 'powertop'. Check 0xE2 and 0xE4 MSR to verify IO/Mwait redirection. Signed-off-by: Ravi Sarawadi Change-Id: I99b66b02eb790b6b348be7c964d21ec9a6926926 Reviewed-on: https://review.coreboot.org/17168 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/cpu.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/apollolake/cpu.c') diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index e67842c369..bd5cff50a9 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -25,11 +25,32 @@ #include #include #include +#include #include +#include #include +static const struct reg_script core_msr_script[] = { + /* Enable C-state and IO/MWAIT redirect */ + REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL, + (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK + | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)), + /* Power Management I/O base address for I/O trapping to C-states */ + REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, + (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + REG_SCRIPT_END +}; + +static void soc_core_init(device_t cpu) +{ + /* Set core MSRs */ + reg_script_run(core_msr_script); +} + static struct device_operations cpu_dev_ops = { - .init = DEVICE_NOOP, + .init = soc_core_init, }; static struct cpu_device_id cpu_table[] = { -- cgit v1.2.3