From ef8deaffcbfb68c5b15cdc9c91607fce5734ec8b Mon Sep 17 00:00:00 2001 From: Vaibhav Shankar Date: Tue, 23 Aug 2016 17:56:17 -0700 Subject: soc/intel/apollolake: Add PM methods to power gate PCIe This implements GNVS variable to store the address of PERST_0, _ON/_OFF methods to power gate PCIe during S0ix entry, and PERST_0 assertion/de-assertion methods. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar Reviewed-on: https://review.coreboot.org/16351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Duncan Laurie Reviewed-by: Paul Menzel --- src/soc/intel/apollolake/chip.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/apollolake/chip.h') diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index a9605b76a8..74a6411b50 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -116,6 +116,9 @@ struct soc_intel_apollolake_config { /* SLP S3 minimum assertion width. */ int slp_s3_assertion_width_usecs; + + /* GPIO pin for PERST_0 */ + uint16_t prt0_gpio; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ -- cgit v1.2.3