From a247d8e53cebbd754e46f76412ed9d17df752308 Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Tue, 27 Sep 2016 23:18:35 +0530 Subject: soc/intel/apollolake: Set PL1 limits for RAPL MSR registers This patch sets the package power limit (PL1) value in RAPL MSR and disables MMIO register. Added configurable PL1 override parameter to leverage full TDP capacity. BUG=chrome-os-partner:56922 TEST=webGL performance(fps) not impacted before and after S3. Change-Id: I34208048a6d4a127e9b1267d2df043cb2c46cf77 Signed-off-by: Sumeet Pawnikar Signed-off-by: Venkateswarlu Vinjamuri Reviewed-on: https://review.coreboot.org/16884 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/chip.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/apollolake/chip.h') diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 74a6411b50..6c3bcd8cad 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -107,6 +107,9 @@ struct soc_intel_apollolake_config { /* Enable DPTF support */ int dptf_enable; + /* PL1 override value in mW for APL */ + uint16_t tdp_pl1_override_mw; + /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] */ -- cgit v1.2.3