From 9a4beb429d87f9c0f46b7f945432a955cd88c962 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Mon, 28 Jan 2019 16:04:35 -0800 Subject: soc/intel/apollolake: Sync fsp upd structure update FSP 2.0.9 provides UPD interface to adjust integrated filter value, usb3 LDO and pmic vdd2 voltage. Change coreboot upd structure to sync with fsp 2.0.9 release. BUG=b:123398358 CQ-DEPEND=CL:*817128 TEST=Verified yorp boots to kernel. Change-Id: I3d17dfbe58bdc5222378459723da8e9ac0573510 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/31131 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/chip.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/soc/intel/apollolake/chip.h') diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9c9dc58ac..6c2404a405 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -168,6 +168,26 @@ struct soc_intel_apollolake_config { * 0:FALSE(Default), 1:True. */ uint8_t DisableComplianceMode; + + /* Options to change USB3 ModPhy setting for the Integrated Filter (IF) + * value. Default is 0 to not changing default IF value (0x12). Set + * value with the range from 0x01 to 0xff to change IF value. + */ + uint8_t ModPhyIfValue; + + /* Options to bump USB3 LDO voltage. Default is FALSE to not increasing + * LDO voltage. Set TRUE to increase LDO voltage with 40mV. + * 0:FALSE (default), 1:True. + */ + uint8_t ModPhyVoltageBump; + + /* Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting + * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage + * configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16) + * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]: + * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default). + */ + uint32_t PmicVdd2Voltage; }; typedef struct soc_intel_apollolake_config config_t; -- cgit v1.2.3