From 88df48c555e31c0c59ac8ff6dffb812a51f57c8b Mon Sep 17 00:00:00 2001 From: Venkateswarlu Vinjamuri Date: Fri, 2 Sep 2016 16:04:27 -0700 Subject: soc/apollolake: Enable/disable Audio clk and power gate in devicetree.cb BUG=chrome-os-partner:56034 Change-Id: Id88d262b32dea468536575117fc34d52076a3096 Signed-off-by: Venkateswarlu Vinjamuri Reviewed-on: https://review.coreboot.org/16423 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/chip.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/soc/intel/apollolake/chip.h') diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 22217a4dea..a9605b76a8 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -107,6 +107,13 @@ struct soc_intel_apollolake_config { /* Enable DPTF support */ int dptf_enable; + /* Configure Audio clk gate and power gate + * IOSF-SB port ID 92 offset 0x530 [5] and [3] + */ + uint8_t hdaudio_clk_gate_enable; + uint8_t hdaudio_pwr_gate_enable; + uint8_t hdaudio_bios_config_lockdown; + /* SLP S3 minimum assertion width. */ int slp_s3_assertion_width_usecs; }; -- cgit v1.2.3