From 428f90afe7ea85aef023d4d799ac18436cbc3aed Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Fri, 2 Dec 2016 18:14:19 +0530 Subject: soc/intel/apollolake: Set PL2 in RAPL register This patch sets the package power limit (PL2) value in RAPL register. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/17699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/chip.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/apollolake/chip.h') diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index dd301067cc..5f8fed9a56 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -100,6 +100,8 @@ struct soc_intel_apollolake_config { /* PL1 override value in mW for APL */ uint16_t tdp_pl1_override_mw; + /* PL2 override value in mW for APL */ + uint16_t tdp_pl2_override_mw; /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] -- cgit v1.2.3