From e673e5c09eebad3efbe19d15d064d131771abc2c Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 30 Oct 2018 15:12:11 -0700 Subject: soc/intel/apollolake: Improve cold boot and S3 resume FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default 100ms to 10ms to improve cold boot and S3 resume performance. BUG=b:118676361 CQ-DEPEND=CL:*703187 TEST=Verified system_resume_firmware_ec time reduction. Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/29363 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/chip.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/soc/intel/apollolake/chip.c') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 9ee6dbb96d..e6904da75f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -567,6 +567,13 @@ static void glk_fsp_silicon_init_params_cb( * has set up. Hence skipping in FSP. */ silconfig->SkipSpiPCP = 1; + + /* + * FSP provides UPD interface to execute IPC command. In order to + * improve boot performance, configure PmicPmcIpcCtrl for PMC to program + * PMIC PCH_PWROK delay. + */ + silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl; #endif } -- cgit v1.2.3