From cad9b631365c0aa3f917455c3dd44edc3e0d21d4 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 20 Jun 2016 16:08:42 -0700 Subject: intel/apollolake: Disable setting of EISS bit in FSP chrome-os-partner:54589 Change-Id: I5bdd417ed2f7ec013aeb8a0d4a9de57b1ad564a1 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/15276 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/chip.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/apollolake/chip.c') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 4fa4ce4b6d..dd4a0a56e8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -138,6 +138,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->P2sbBase = P2SB_BAR; silconfig->IshEnable = cfg->integrated_sensor_hub_enable; + + /* Disable setting of EISS bit in FSP. */ + silconfig->SpiEiss = 0; } struct chip_operations soc_intel_apollolake_ops = { -- cgit v1.2.3