From ba3d626cfbc5b0ba4dcbdf756a3abf5e61afa210 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Fri, 24 Jun 2016 10:41:39 -0700 Subject: soc/intel/apollolake: Update Upd header files for FSP Label 143_10 New UPDs added to header files as well as many comment fixes. Memory infor is now defined in FspmUpd.h and added ability to skip CSE RBP for coreboot. Removes some UPDs that are no longer available from source. BUG=chrome-os-partner:54677 BRANCH=none TEST=built and tested with FSP 143_10 version Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/15459 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/chip.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'src/soc/intel/apollolake/chip.c') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 821570bfe8..044ef913b9 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -253,12 +253,6 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) if (cfg->emmc_rx_cmd_data_cntl2 != 0) silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; - /* Our defaults may not match FSP defaults, so set them explicitly */ - silconfig->AcpiBase = ACPI_PMIO_BASE; - /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ - silconfig->PmcBase = PMC_BAR0 + 0x1000; - silconfig->P2sbBase = P2SB_BAR; - silconfig->IshEnable = cfg->integrated_sensor_hub_enable; /* Disable setting of EISS bit in FSP. */ -- cgit v1.2.3