From ad62b9af651eddf78fd6db37a32f99f429019324 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 30 Jan 2019 22:47:17 -0800 Subject: soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables GLK has a dedicated USB2 port that is used specifically for CNVi BT. This requires that the ACPI tables define an additional USB 2 port which results in _ADR for USB 3 ports being different for GLK than APL. This change splits the ports in xhci.asl into APL and GLK specific ports.asl and selects the appropriate file based on CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK if ACPI name is requested for that port. BUG=b:123670712 BRANCH=octopus TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and for reef (APL) does not include HS09 definition. Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/31172 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/chip.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/apollolake/chip.c') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index cddfe4436f..de33e8217b 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -121,6 +121,9 @@ const char *soc_acpi_name(const struct device *dev) case 5: return "HS06"; case 6: return "HS07"; case 7: return "HS08"; + case 8: + if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + return "HS09"; } break; case 3: -- cgit v1.2.3