From 9116eb660eac5fe906f8968704f3daa739c1a8e9 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Thu, 23 Aug 2018 11:39:19 +0200 Subject: soc/intel/apollolake: Make eMMC max speed configurable The eMMC maximum speed is set to HS400 mode per default. To increase the lifetime of the circuit, it is necessary to reduce the eMMC speed. Change-Id: I6fa5eb56a0593e24269ef143645c506232879889 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/28282 Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/chip.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/apollolake/chip.c') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 9b8cfd7bcf..4ea89710ab 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 - 2017 Intel Corp. - * Copyright (C) 2017 Siemens AG + * Copyright (C) 2017 - 2018 Siemens AG * (Written by Alexandru Gagniuc for Intel Corp.) * (Written by Andrey Petrov for Intel Corp.) * @@ -616,6 +616,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl; if (cfg->emmc_rx_cmd_data_cntl2 != 0) silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; + if (cfg->emmc_host_max_speed != 0) + silconfig->eMMCHostMaxSpeed = cfg->emmc_host_max_speed; silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; -- cgit v1.2.3