From 4b966b57edef3a9b4d85abf406d433cfbb415729 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Wed, 21 Sep 2022 08:52:42 +0100 Subject: soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown Configure FSP S UPDs to allow coreboot to handle the lockdown. The main change here is setting `Write Protection Support` to 0, as the default is Enabled, which shouldn't allow writes (even though it seems to). The UPDs are identical on APL and GLK, but all ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes Change-Id: I1f6e5344cab2af7aa6001b9ec0f07b043a9caa8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67754 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/apollolake/chip.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'src/soc/intel/apollolake/chip.c') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index da2d00adb7..607c1746ff 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -697,11 +697,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); - /* Disable setting of EISS bit in FSP. */ - silconfig->SpiEiss = 0; - - /* Disable FSP from locking access to the RTC NVRAM */ - silconfig->RtcLock = 0; + /* coreboot handles the lockdown */ + silconfig->LockDownGlobalSmi = 0; + silconfig->BiosLock = 0; + silconfig->BiosInterface = 0; + silconfig->WriteProtectionEnable[0] = 0; + silconfig->SpiEiss = 0; + silconfig->RtcLock = 0; /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; -- cgit v1.2.3