From 4520c5e757cf280b7029a99adff60baed52493ce Mon Sep 17 00:00:00 2001
From: Andrey Petrov <andrey.petrov@intel.com>
Date: Mon, 18 Apr 2016 13:36:19 -0700
Subject: soc/intel/apollolake: Configure a GPIO for TPM in bootblock

One of devices connected to FAST SPI bus is TPM. SoC uses dedicated
line for chip select for TPM function. If TPM is used, that line needs
to be configured to a specific native funciton.

Change-Id: Ib5bf4c759adf9656f7b34540d4fc924945d27a97
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14467
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/apollolake/bootblock/bootblock.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'src/soc/intel/apollolake/bootblock')

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index c65571490b..be07776f19 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -19,10 +19,21 @@
 #include <device/pci.h>
 #include <soc/bootblock.h>
 #include <soc/cpu.h>
+#include <soc/gpio.h>
 #include <soc/northbridge.h>
 #include <soc/pci_devs.h>
 #include <soc/uart.h>
 
+static const struct pad_config tpm_spi_configs[] = {
+	PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3),	/* FST_SPI_CS2_N */
+};
+
+static void tpm_enable(void)
+{
+	/* Configure gpios */
+	gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
+}
+
 void asmlinkage bootblock_c_entry(void)
 {
 	device_t dev = NB_DEV_ROOT;
@@ -45,4 +56,7 @@ void bootblock_soc_early_init(void)
 	/* Prepare UART for serial console. */
 	if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
 		soc_console_uart_init();
+
+	if (IS_ENABLED(CONFIG_LPC_TPM))
+		tpm_enable();
 }
-- 
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