From 8d66bee7beddfefcd493b232ff832f6d3053f9a5 Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@google.com>
Date: Sat, 30 Jul 2016 18:06:23 -0700
Subject: intel/apollolake: Enable upper CMOS bank in bootblock

Upper CMOS bank is used to store the boot count. It is important to
enable it as soon as possible in bootblock.

BUG=chrome-os-partner:55473

Change-Id: I7c4f49c337c2e24a93c1e71466e2f66db04be562
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15998
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
 src/soc/intel/apollolake/bootblock/bootblock.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src/soc/intel/apollolake/bootblock/bootblock.c')

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 31144ff219..3015d17079 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -22,6 +22,7 @@
 #include <soc/iomap.h>
 #include <soc/cpu.h>
 #include <soc/gpio.h>
+#include <soc/iosf.h>
 #include <soc/mmap_boot.h>
 #include <soc/northbridge.h>
 #include <soc/pci_devs.h>
@@ -56,6 +57,13 @@ static void enable_pm_timer(void)
 	wrmsr(MSR_EMULATE_PM_TMR, msr);
 }
 
+static void enable_cmos_upper_bank(void)
+{
+	uint32_t reg = iosf_read(IOSF_RTC_PORT_ID, RTC_CONFIG);
+	reg |= RTC_CONFIG_UCMOS_ENABLE;
+	iosf_write(IOSF_RTC_PORT_ID, RTC_CONFIG, reg);
+}
+
 void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
 {
 	device_t dev = NB_DEV_ROOT;
@@ -82,6 +90,8 @@ void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
 	pci_write_config16(dev, PCI_COMMAND,
 				PCI_COMMAND_IO | PCI_COMMAND_MASTER);
 
+	enable_cmos_upper_bank();
+
 	/* Call lib/bootblock.c main */
 	bootblock_main_with_timestamp(base_timestamp);
 }
-- 
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