From f03c63ef956b53c691567e0bc3a4b61357155755 Mon Sep 17 00:00:00 2001 From: Venkateswarlu Vinjamuri Date: Thu, 12 Apr 2018 10:13:43 -0700 Subject: soc/intel/apollolake: Configure PCIe root port #3 for GLK WiFi GLK Octopus uses PCIe root port #3 (PCIe ID 13.0) for discrete PCIe wifi card. BUG=None BRANCH=None TEST=Use Stone Peak discrete wifi card and test s0ix. Change-Id: I8a064c5d97e4765bd97ec560c89b207b574b1fa1 Signed-off-by: Venkateswarlu Vinjamuri Reviewed-on: https://review.coreboot.org/25638 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/acpi/pcie.asl | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/apollolake/acpi') diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl index da9959123a..539ae9b71e 100644 --- a/src/soc/intel/apollolake/acpi/pcie.asl +++ b/src/soc/intel/apollolake/acpi/pcie.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,3 +22,11 @@ Device (RP01) #include "pcie_port.asl" } + +Device (RP03) +{ + Name (_ADR, 0x00130000) + Name (_DDN, "PCIe-A 0") + + #include "pcie_port.asl" +} -- cgit v1.2.3