From 1bd0c0c4971ce50426cbe18e93e2ec9dca320af1 Mon Sep 17 00:00:00 2001 From: Lance Zhao Date: Tue, 19 Apr 2016 18:04:21 -0700 Subject: soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/acpi/globalnvs.asl | 35 +++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 src/soc/intel/apollolake/acpi/globalnvs.asl (limited to 'src/soc/intel/apollolake/acpi') diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl new file mode 100644 index 0000000000..2ef5031ebf --- /dev/null +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * NOTE: The layout of the GNVS structure below must match the layout in + * soc/intel/apollolake/include/soc/nvs.h !!! + * + */ + +External (NVSA) + +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Nothing here yet, folks */ + Offset (0x00), + + /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ + Offset (0x100), + #include +} -- cgit v1.2.3