From ad62b9af651eddf78fd6db37a32f99f429019324 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 30 Jan 2019 22:47:17 -0800 Subject: soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables GLK has a dedicated USB2 port that is used specifically for CNVi BT. This requires that the ACPI tables define an additional USB 2 port which results in _ADR for USB 3 ports being different for GLK than APL. This change splits the ports in xhci.asl into APL and GLK specific ports.asl and selects the appropriate file based on CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK if ACPI name is requested for that port. BUG=b:123670712 BRANCH=octopus TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and for reef (APL) does not include HS09 definition. Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/31172 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/acpi/xhci.asl | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) (limited to 'src/soc/intel/apollolake/acpi/xhci.asl') diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index 9f8503341d..9f7304bb57 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -34,22 +34,10 @@ Device (XHCI) { /* Root Hub */ Name (_ADR, Zero) - /* USB2 */ - Device (HS01) { Name (_ADR, 1) } - Device (HS02) { Name (_ADR, 2) } - Device (HS03) { Name (_ADR, 3) } - Device (HS04) { Name (_ADR, 4) } - Device (HS05) { Name (_ADR, 5) } - Device (HS06) { Name (_ADR, 6) } - Device (HS07) { Name (_ADR, 7) } - Device (HS08) { Name (_ADR, 8) } - - /* USB3 */ - Device (SS01) { Name (_ADR, 9) } - Device (SS02) { Name (_ADR, 10) } - Device (SS03) { Name (_ADR, 11) } - Device (SS04) { Name (_ADR, 12) } - Device (SS05) { Name (_ADR, 13) } - Device (SS06) { Name (_ADR, 14) } +#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#include "xhci_glk_ports.asl" +#else +#include "xhci_apl_ports.asl" +#endif } } -- cgit v1.2.3