From d6463dd42c0b5688601ce6de5e7cff16926df297 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Wed, 25 May 2016 11:34:43 -0700 Subject: intel/apollolake: Add support to enable google ChromeEC ChromeEC is needed for EC controlled features to work properly. This patch adds neccessary support in soc/intel so that mainboard asl files can include the ChromeEC e.g. PNOT method and LPCB and also the nvs fields. BUG = 53096 TEST = This patch is needed by the mainboard specific ASL change to include src/ec/google/chromeec/acpi/ec.asl Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9 Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/14967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/acpi/globalnvs.asl | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/apollolake/acpi/globalnvs.asl') diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031ebf..e081dcb60b 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -26,8 +26,13 @@ External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { - /* Nothing here yet, folks */ + /* Miscellaneous */ Offset (0x00), + PCNT, 8, // 0x01 - Processor Count + PPCM, 8, // 0x02 - Max PPC State + LIDS, 8, // 0x03 - LID State + PWRS, 8, // 0x04 - AC Power State + DPTE, 8, // 0x05 - Enable DPTF /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), -- cgit v1.2.3