From ef8deaffcbfb68c5b15cdc9c91607fce5734ec8b Mon Sep 17 00:00:00 2001 From: Vaibhav Shankar Date: Tue, 23 Aug 2016 17:56:17 -0700 Subject: soc/intel/apollolake: Add PM methods to power gate PCIe This implements GNVS variable to store the address of PERST_0, _ON/_OFF methods to power gate PCIe during S0ix entry, and PERST_0 assertion/de-assertion methods. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar Reviewed-on: https://review.coreboot.org/16351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Duncan Laurie Reviewed-by: Paul Menzel --- src/soc/intel/apollolake/acpi.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel/apollolake/acpi.c') diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 1ca04fd3fe..5718d7eba0 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "chip.h" #define CSTATE_RES(address_space, width, offset, address) \ @@ -175,6 +176,10 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) /* Enable DPTF based on mainboard configuration */ gnvs->dpte = cfg->dptf_enable; + + /* Assign address of PERST_0 if GPIO is defined in devicetree */ + if (cfg->prt0_gpio != GPIO_PRT0_UDEF) + gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio); } /* Save wake source information for calculating ACPI _SWS values */ -- cgit v1.2.3