From 08769c6d1404c1be0333273d8b988544750ce87d Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Mon, 9 May 2022 14:33:15 +0200
Subject: soc/intel/*: Use SSDT to pass A4GB and A4GS

GNVS is more fragile as you need to keep struct elements in sync with
ASL code.

Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/apollolake/acpi.c | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'src/soc/intel/apollolake/acpi.c')

diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 0e60771207..e0e6163b49 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -86,9 +86,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 		gnvs->scdp = gpio_get_pad_portid(cfg->sdcard_cd_gpio);
 		gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio);
 	}
-
-	/* Fill in Above 4GB MMIO resource */
-	sa_fill_gnvs(gnvs);
 }
 
 int soc_madt_sci_irq_polarity(int sci)
-- 
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