From ff8bce0a5f53652d4d26cb501159e8711f79eb9b Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 27 Jun 2016 10:57:13 -0700 Subject: soc/intel/apollolake: Add support for LPSS I2C driver Support the I2C interfaces on this SOC using the Intel common lpss_i2c driver. The controllers are supported in pre-ram environments by setting a temporary base address in bootblock and in ramstage using the naturally enumerated base address. The base speed of this controller is 133MHz and the SCL/SDA timing values that are reported to the OS are calculated using that clock. This was tested on a google/reef board doing I2C transactions to the trackpad both in verstage and in ramstage. Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/15480 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/apollolake/Makefile.inc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 030e35cc1a..a64ee78328 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -23,6 +23,7 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c +romstage-y += i2c_early.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += lpc_lib.c romstage-y += memmap.c @@ -45,6 +46,7 @@ ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += gpio.c ramstage-y += graphics.c +ramstage-y += i2c.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += lpc.c ramstage-y += lpc_lib.c @@ -69,6 +71,7 @@ postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c verstage-y += car.c +verstage-y += i2c_early.c verstage-y += memmap.c verstage-y += mmap_boot.c verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c -- cgit v1.2.3