From b66757fc58b9bd025148d9db690009dec487fd0d Mon Sep 17 00:00:00 2001 From: Praveen hodagatta pranesh Date: Tue, 23 Oct 2018 02:43:05 +0800 Subject: soc/intel: Consolidate FSP CAR setup and teardown code This patch adds following changes, - APL, CFL, DENVERTON soc's using same implementation to setup and teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is cosolidated into one file and moved to common code CPU car folder. - exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file and moved to common CPU car. - The new file apollolake/fspcar.c is addded to pass tempraminit parameters. - Coffee lake Soc uses FSPT to support Intel Security features like BootGuard verify boot and Measured boot. Add FSP CAR support for CFL by programming tempraminit parameters and add FSP_T_XIP default if FSP_CAR is selected. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup. Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR without errors. Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9 Signed-off-by: Praveen hodagatta pranesh Reviewed-on: https://review.coreboot.org/29209 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/Makefile.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/soc/intel/apollolake/Makefile.inc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index ede565ae37..6168f86449 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c +bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += car.c bootblock-y += heci.c bootblock-y += gspi.c @@ -18,7 +19,6 @@ bootblock-y += mmap_boot.c bootblock-y += pmutil.c bootblock-y += spi.c bootblock-$(CONFIG_UART_DEBUG) += uart.c -bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c @@ -76,8 +76,6 @@ postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c postcar-$(CONFIG_UART_DEBUG) += uart.c -postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S - verstage-y += car.c verstage-y += i2c.c verstage-y += gspi.c -- cgit v1.2.3