From b54a2d1d76549fc6dfacb880439d8785a50a589f Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 1 Jun 2016 01:55:43 -0700 Subject: intel/apollolake: Add car.c to verstage Verstage on apollolake requires the functions defined in car.c to perform flush of l1d to l2 on loading romstage into CAR. Change-Id: I6d9a0b9dfb58c2126ad70172846e90663e588857 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/15046 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/apollolake/Makefile.inc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 29636e17b8..9e4e160e35 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -59,6 +59,7 @@ postcar-y += mmap_boot.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c +verstage-y += car.c verstage-y += memmap.c verstage-y += mmap_boot.c verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c -- cgit v1.2.3