From b13bd1efcf568bb220500ca94e4de097f3bed9ec Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 21 Sep 2020 22:44:27 +0000 Subject: Revert "soc/intel: Refactor do_global_reset() function" This reverts commit 77cc3267fc970c710299a164ecbc471f9287d719. Reason for revert: Breaks quark and also needs breaking down into multiple CLs as commented by Nico on CB:45541 Change-Id: Idf4ca74158df15483856754ee24cc4472a8e09b0 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/44997 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons Reviewed-by: Subrata Banik --- src/soc/intel/apollolake/Makefile.inc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel/apollolake/Makefile.inc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index b9d302c1e4..79fab1a9d1 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -12,6 +12,7 @@ subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += car.c +bootblock-y += heci.c bootblock-y += gspi.c bootblock-y += i2c.c bootblock-y += lpc.c @@ -25,6 +26,7 @@ romstage-y += ../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += report_platform.c romstage-y += gspi.c +romstage-y += heci.c romstage-y += i2c.c romstage-y += uart.c romstage-y += meminit.c @@ -54,6 +56,7 @@ ramstage-y += cse.c ramstage-y += elog.c ramstage-y += graphics.c ramstage-y += gspi.c +ramstage-y += heci.c ramstage-y += i2c.c ramstage-y += lpc.c ramstage-y += mmap_boot.c @@ -72,6 +75,7 @@ ramstage-y += xhci.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-y += i2c.c +postcar-y += heci.c postcar-y += reset.c postcar-y += uart.c postcar-y += gspi.c @@ -79,6 +83,7 @@ postcar-y += gspi.c verstage-y += car.c verstage-y += i2c.c verstage-y += gspi.c +verstage-y += heci.c verstage-y += mmap_boot.c verstage-y += uart.c verstage-y += pmutil.c -- cgit v1.2.3