From aaf28d2507336b809b4420841b537652487439bd Mon Sep 17 00:00:00 2001 From: Usha P Date: Mon, 17 Feb 2020 15:14:18 +0530 Subject: soc/intel/apollolake: Display platform information This patch includes the change required to display Apollo Lake platform information which reports CPU, MCH, PCH and IGD information in romstage. BUG=None TEST= 1. Boot to OS on Bobba board. 2. Verified below info from CPU Console log in romstage CPU: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz CPU: ID 706a1, Geminilake B0, ucode: 00000031 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 31f0 (rev 03) is Geminilake PCH: device id 3197 (rev 03) is Geminilake IGD: device id 3185 (rev 03) is Geminilake EU12 Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/38824 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/apollolake/Makefile.inc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1fbdc91c72..b420dea64d 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -24,6 +24,7 @@ bootblock-y += uart.c romstage-y += car.c romstage-y += ../../../cpu/intel/car/romstage.c romstage-y += romstage.c +romstage-y += report_platform.c romstage-y += gspi.c romstage-y += heci.c romstage-y += i2c.c -- cgit v1.2.3