From 1799011dc6914927d951cc076a405c6b20ead5d5 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 27 Aug 2019 11:01:33 +0530 Subject: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code This patch includes common romstage code to setup the console and load postcar. Fix booting regression issue on all latest IA-SOC introduced by CB:34893 Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/35109 Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar Reviewed-by: Maulik V Vaghela Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/apollolake/Makefile.inc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 60b1a3c4f5..41faf7243b 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -21,6 +21,7 @@ bootblock-y += spi.c bootblock-y += uart.c romstage-y += car.c +romstage-y += ../../../cpu/intel/car/romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gspi.c romstage-y += heci.c -- cgit v1.2.3