From 1318e88352d7b20661adec82769f46308471d739 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 12 Jul 2016 23:39:51 -0500 Subject: soc/intel/apollolake: add initial ITSS support The interrupt and timer subsystem (ITSS) sits between the APIC and the other logic blocks. It only supports positive polarity events, but there's a polarity inversion setting for each IRQ such that it can pass the signal on to the APIC according to the expected APIC redirection entry values. This support is needed in order for the platform/board to set the expected interrupt polarity into the APIC for gpio signals. BUG=chrome-os-partner:54955 Change-Id: I50ea1b7c4a7601e760878af515518cc0e808c0d1 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15647 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Andrey Petrov Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/apollolake/Makefile.inc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 8dacdabbd5..c44fc464d5 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -13,6 +13,7 @@ bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c bootblock-y += gpio.c +bootblock-y += itss.c bootblock-y += lpc_lib.c bootblock-y += mmap_boot.c bootblock-y += pmutil.c @@ -24,6 +25,7 @@ romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c romstage-y += i2c_early.c +romstage-y += itss.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += lpc_lib.c romstage-y += memmap.c @@ -48,6 +50,7 @@ ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += i2c.c +ramstage-y += itss.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += lpc.c ramstage-y += lpc_lib.c -- cgit v1.2.3