From 0f718312f1b57ec300b7486c95e53562be5a2325 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 3 Jul 2019 13:02:37 -0600 Subject: soc/intel/common: Add SOC specific function to get XHCI USB info It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required. BUG=None BRANCH=None TEST=Boot to ChromeOS. Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290 Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/apollolake/Makefile.inc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4fc16d5891..6fd0822109 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -44,6 +44,7 @@ smm-y += smihandler.c smm-y += spi.c smm-y += uart.c smm-y += elog.c +smm-y += xhci.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c @@ -67,6 +68,7 @@ ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += xdci.c ramstage-y += sd.c +ramstage-y += xhci.c postcar-y += memmap.c postcar-y += mmap_boot.c -- cgit v1.2.3