From eebe0e0db14476dde980896b8eb8a97129436af3 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 18 Mar 2016 11:19:38 -0500 Subject: soc/intel/apollolake: utilize postcar phase/stage The current Apollolake flow has its code executing out of cache-as-ram for the pre-DRAM stages. This is different from past platforms where they were just executing-in-place against the memory-mapped SPI flash boot media. The implication is that when cache-as-ram needs to be torn down one needs to be executing out of DRAM since the act of cache-as-ram going away means the code disappears out from under the processor. Therefore load and use the postcar infrastructure to bootstrap this process for tearing down cache-as-ram and subsequently loading ramstage. Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/14141 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/apollolake/Kconfig') diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a11c5a28d6..efebe513c2 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE + select POSTCAR_STAGE select REG_SCRIPT select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select SOC_INTEL_COMMON -- cgit v1.2.3