From 4ed9f9a507a8b3419bc45431b8f1afb02c728a9e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 31 Oct 2020 22:01:55 +0530 Subject: soc/intel: Use of common reset code block This patch removes all redundant reset code block from each SoC and make use of common reset code block(fsp_reset.c) based on SOC_INTEL_COMMON_FSP_RESET. Respective SoC Kconfig to choose correct FSP global reset type as per FSP integration guide. Signed-off-by: Subrata Banik Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/apollolake/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/apollolake/Kconfig') diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0c8eae2264..3917feaf79 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS # Misc options select CACHE_MRC_SETTINGS select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS + select FSP_STATUS_GLOBAL_RESET_REQUIRED_5 select GENERIC_GPIO_LIB select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER @@ -91,6 +92,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_FSP_RESET select SOUTHBRIDGE_INTEL_COMMON_SMBUS select UDELAY_TSC select TSC_MONOTONIC_TIMER -- cgit v1.2.3