From ee449451878ad41caa8724d6435f32c1af474d7b Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Fri, 8 Apr 2022 14:36:13 +0530 Subject: soc/intel/alderlake: Add support enable external V1P05/Vnn rails This patch adds the support to enable the external V1P05/Vnn rails in S0 state via devicetree. BUG=b:223102016 Signed-off-by: V Sowmya Change-Id: I555e5607af15a5f5d83ef74321b1b71f17cca289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63497 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Kangheui Won --- src/soc/intel/alderlake/chip.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 7934a8635a..665a68c100 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -82,7 +82,7 @@ enum ddi_port_flags { /* * Enable External V1P05/Vnn/VnnSx Rail in: BIT0:S0i1/S0i2, - * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 + * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5, BIT5:S0. */ enum fivr_enable_states { FIVR_ENABLE_S0i1_S0i2 = BIT(0), @@ -90,6 +90,7 @@ enum fivr_enable_states { FIVR_ENABLE_S3 = BIT(2), FIVR_ENABLE_S4 = BIT(3), FIVR_ENABLE_S5 = BIT(4), + FIVR_ENABLE_S0 = BIT(5), }; /* @@ -107,7 +108,7 @@ enum fivr_voltage_supported { }; #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \ - FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5) + FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5 | FIVR_ENABLE_S0) /* * The Max Pkg Cstate * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, -- cgit v1.2.3