From dccfb8a2158287be48522f9f70fd3e83b84c671f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 7 Apr 2022 15:09:19 +0200 Subject: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Intel DOC #630603 P2SB BAR must be at 0xe0000000 for PCH-S. Signed-off-by: Michał Żygowski Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63460 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b63162465f..35fd2f710f 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -251,6 +251,7 @@ config SMM_RESERVED_SIZE config PCR_BASE_ADDRESS hex + default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S default 0xfd000000 help This option allows you to select MMIO Base Address of sideband bus. -- cgit v1.2.3