From db925aaf38dfc10de74c80cb1e43a7058fa8811a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 1 Dec 2021 11:44:09 +0100 Subject: soc/intel/alderlake: Add Kconfigs for all PCH types The Alder Lake code currently supports the PCH-M and PCH-P types, which have some differences (so far, only the amount of PCIe I/O). Mainboards can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which PCH type they use: select the option to choose PCH-M, do not select the option to choose PCH-P. While this works, it can be confusing once more PCH types are added. Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards have to explicitly choose a PCH type. Also, use this option to restrict the PCH-P defaults for PCH-dependent settings to avoid unintended reuse of the PCH-P defaults when adding a new PCH type. To make sure only one PCH type is selected, add some preprocessor in `bootblock.h` to provoke a build-time error if this requirement is not met. Kconfig doesn't seem to have a mechanism to describe sets of mutually-exclusive bool options that allows said options to be selected (a `choice` block doesn't allow its elements to be selected). Finally, adapt the ADL boards accordingly. Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: EricR Lai --- src/soc/intel/alderlake/Kconfig | 23 ++++++++++++++++------- src/soc/intel/alderlake/include/soc/bootblock.h | 5 +++++ 2 files changed, 21 insertions(+), 7 deletions(-) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index e5d6d6b999..2f8f3da429 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -1,12 +1,21 @@ config SOC_INTEL_ALDERLAKE bool help - Intel Alderlake support + Intel Alderlake support. Mainboards should specify the PCH + type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead + of selecting this option directly. config SOC_INTEL_ALDERLAKE_PCH_M bool + select SOC_INTEL_ALDERLAKE help - Choose this option if you have PCH-M chipset. + Choose this option if your mainboard has a PCH-M chipset. + +config SOC_INTEL_ALDERLAKE_PCH_P + bool + select SOC_INTEL_ALDERLAKE + help + Choose this option if your mainboard has a PCH-P chipset. if SOC_INTEL_ALDERLAKE @@ -169,12 +178,12 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config MAX_PCH_ROOT_PORTS int default 10 if SOC_INTEL_ALDERLAKE_PCH_M - default 12 + default 12 if SOC_INTEL_ALDERLAKE_PCH_P config MAX_CPU_ROOT_PORTS int default 1 if SOC_INTEL_ALDERLAKE_PCH_M - default 3 + default 3 if SOC_INTEL_ALDERLAKE_PCH_P config MAX_ROOT_PORTS int @@ -183,12 +192,12 @@ config MAX_ROOT_PORTS config MAX_PCIE_CLOCK_SRC int default 6 if SOC_INTEL_ALDERLAKE_PCH_M - default 7 + default 7 if SOC_INTEL_ALDERLAKE_PCH_P config MAX_PCIE_CLOCK_REQ int - default 6 if SOC_INTEL_ALDERLAKE_PCH_M - default 10 + default 6 if SOC_INTEL_ALDERLAKE_PCH_M + default 10 if SOC_INTEL_ALDERLAKE_PCH_P config SMM_TSEG_SIZE hex diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h index 0cf334fe09..059568d09b 100644 --- a/src/soc/intel/alderlake/include/soc/bootblock.h +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -3,6 +3,11 @@ #ifndef _SOC_ALDERLAKE_BOOTBLOCK_H_ #define _SOC_ALDERLAKE_BOOTBLOCK_H_ +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \ + CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1 +#error "Please select exactly one PCH type" +#endif + /* Bootblock pre console init programming */ void bootblock_pch_early_init(void); -- cgit v1.2.3