From d6b763ca634163c9d8b9afca51f88698704c0fa9 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 27 Jul 2022 09:53:58 -0600 Subject: soc/intel/alderlake: Add support for more CPU PCIe RP UPDs There are 3 more CPU PCIe RP UPDs that are the current code is not setting, and some boards may want to set these, so this patch adds support to set these UPDs. The default values for any existing boards using these UPDs should not change with this patch. The UPDs are: - CpuPcieRpDetectTimeoutMs - CpuPcieRpAspm - CpuPcieRpSlotImplemented Signed-off-by: Tim Wawrzynczak Change-Id: Id48019f984e8e53ff3ce0c3c23e02dab65112c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66197 Reviewed-by: Lean Sheng Tan Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/fsp_params.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 19040d8651..b4482512ad 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -895,7 +895,13 @@ static void fill_fsps_cpu_pcie_params(FSP_S_CONFIG *s_cfg, s_cfg->CpuPcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); + s_cfg->CpuPcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; s_cfg->PtmEnabled[i] = 0; + if (rp_cfg->pcie_rp_aspm) + s_cfg->CpuPcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); + + if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN)) + s_cfg->CpuPcieRpSlotImplemented[i] = 0; } s_cfg->CpuPcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); } -- cgit v1.2.3