From cffc938934a9ee3b344ef594874e55f131bea77b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 29 Jan 2021 18:41:35 +0530 Subject: soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip). ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip). Change-Id: I7d223c165f819669722cbc80245fa8ec20372352 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130 Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/Kconfig | 11 ++++++++--- src/soc/intel/alderlake/chip.h | 4 ++-- 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 7289e02032..806c91b334 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -139,10 +139,15 @@ config MAX_ROOT_PORTS int default MAX_PCH_ROOT_PORTS -config MAX_PCIE_CLOCKS +config MAX_PCIE_CLOCK_SRC int - default 10 if SOC_INTEL_ALDERLAKE_PCH_M - default 12 + default 6 if SOC_INTEL_ALDERLAKE_PCH_M + default 7 + +config MAX_PCIE_CLOCK_REQ + int + default 6 if SOC_INTEL_ALDERLAKE_PCH_M + default 10 config SMM_TSEG_SIZE hex diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 70ceba7fdf..0f932ce132 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -131,10 +131,10 @@ struct soc_intel_alderlake_config { /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ - uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; + uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to * clksrc. */ - uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_REQ]; /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS]; -- cgit v1.2.3