From ca5254acc0d55199254a270496c955249ad244d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 14 Feb 2024 13:23:28 +0100 Subject: soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set. Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD as well for Alder Lake. Setting this FSP-M UPD will cause FSP to properly program sideband use BSSB_LSx pins for the enabled Type-C ports. Required for proper DCI debug and TCSS initialization flow. Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/80500 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/alderlake/romstage/fsp_params.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 84f83e3bbe..d917e6cdfe 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -271,6 +271,11 @@ static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0); m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1); + m_cfg->UsbTcPortEnPreMem = 0; + for (int i = 0; i < MAX_TYPE_C_PORTS; i++) + if (config->tcss_ports[i].enable) + m_cfg->UsbTcPortEnPreMem |= BIT(i); + #if (CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)) || \ (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) && CONFIG(FSP_USE_REPO)) m_cfg->DisableDynamicTccoldHandshake = -- cgit v1.2.3