From c8b9608154522c38dbd47c09aa08585f1b667c05 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 4 Nov 2022 22:14:38 +0530 Subject: soc/intel: Use `PWRMBASE` over static `Index 0` for PMC This patch replaces static index 0 for PMC read resources with PCI configuration offset 0x10 (PWRMBASE). TEST=Able to build and boot Google, Rex to OS. Without this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 With this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik Change-Id: Iee2523876a8045e70effd5824afc327d1113038b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/soc/intel/alderlake/pmc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index 87cc54a4f8..c28ee2d0a4 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -85,7 +85,8 @@ static void soc_pmc_read_resources(struct device *dev) struct resource *res; /* Add the fixed MMIO resource */ - mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB); /* Add the fixed I/O resource */ res = new_resource(dev, 1); -- cgit v1.2.3