From be5dc3daa00414ae04b1801f59142245e0e4d17f Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Wed, 28 Apr 2021 15:02:47 +0530 Subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64 A DDR5 DIMM internally has two channels each of width 32 bit. But the total physical channel width is 64 bit. BUG=b:180458099 TEST=Boot DDR5 to kernel Signed-off-by: Meera Ravindranath Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52730 Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/soc/intel/alderlake/meminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index d40ee35e73..8b5e0071ef 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -11,7 +11,7 @@ #define DDR4_PHYSICAL_CH_WIDTH 64 #define DDR4_CHANNELS CHANNEL_COUNT(DDR4_PHYSICAL_CH_WIDTH) -#define DDR5_PHYSICAL_CH_WIDTH 32 +#define DDR5_PHYSICAL_CH_WIDTH 64 /* 32*2 */ #define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH) static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg) -- cgit v1.2.3