From b544fe48af76e5aae7537d95b62191e1fed2bc45 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 28 Oct 2020 13:25:06 +0530 Subject: mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg' List of changes: 1. Split mem_cfg for DDR4 and LPDDR4 as per board_id 2. Move dq_pins_interleaved into board-specific memory configuration information TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs. Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46873 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/include/soc/meminit.h | 6 ++++++ src/soc/intel/alderlake/meminit.c | 1 + 2 files changed, 7 insertions(+) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 76930be0e7..5fed5680c6 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -76,6 +76,12 @@ struct mb_cfg { /* Rcomp target values. */ uint16_t rcomp_targets[5]; + /* + * Dqs Pins Interleaved Setting. Enable/Disable Control + * TRUE = enable, FALSE = disable + */ + bool dq_pins_interleaved; + /* * Early Command Training Enable/Disable Control * TRUE = enable, FALSE = disable diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index e7084a5a16..f5f747d79b 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -180,4 +180,5 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg, mem_cfg->ECT = board_cfg->ect; mem_cfg->UserBd = board_cfg->UserBd; + mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; } -- cgit v1.2.3