From b2e8bd83647f664260120fdfc7d07cba694dd89e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 17 Nov 2021 15:35:05 +0530 Subject: soc/intel/alderlake: Hook up common code for thermal configuration Thermal configuration registers are now located behind PMC PWRMBASE for Alder Lake Point PCH. Hence, ADL SoC to select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to let thermal low threshold is being set as per mainboard provided `pch_thermal_trip`. Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. BUG=b:193774296 TEST=Dump thermal configuration registers PWRMBASE+0x150c etc. prior to FSP-S shows that registers are now programmed based on 'pch_thermal_trip' and lock register BIT31 is set. Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/59271 Reviewed-by: Felix Singer Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/Kconfig | 1 + src/soc/intel/alderlake/romstage/romstage.c | 11 +++++++++++ 2 files changed, 12 insertions(+) (limited to 'src/soc/intel/alderlake') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 58b9051e6d..2cbff0010d 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -68,6 +68,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index d7ef14d11f..e84eca8ed4 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -127,6 +128,16 @@ void mainboard_romstage_entry(void) heci_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; + + /* + * Set low maximum temp threshold value used for dynamic thermal sensor + * shutdown consideration. + * + * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the + * thermal sensor when CPU is in a C-state and LTT >= DTS Temp. + */ + pch_thermal_configuration(); + fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) { -- cgit v1.2.3